Beremiz-Devel

[Beremiz-devel] Issue with Beremiz ST code generator

Classic

List

Threaded

8 messages Options

Beremiz-Devel mailing list

[Beremiz-devel] Issue with Beremiz ST code generator

Hello everyone!

A user in the openplcproject.com forum reported an issue with the ST code generator for programs with parallel outputs. After a few tests, I could reproduce the issue with this simple program:

out mem out

|-----[ / ]-----[ / ]------------+------( S )------|

| mem

|------( S )------|

(If the diagram doesn't show properly on your email, copy and paste it to notepad).

This program has two boolean variables (out, mem) that are connected in series. If both of them are false, the program sets both to true on a parallel output.

The problem is that the ST code generated by Beremiz (PLCopen Editor) for this program is:

PROGRAM My_Program

VAR

Mem AT %QX99.0 : BOOL;

Out AT %QX0.0 : BOOL;

END_VAR

IF NOT(Mem) AND NOT(Out) THEN

Out := TRUE; (*set*)

END_IF;

IF NOT(Mem) AND NOT(Out) THEN

Mem := TRUE; (*set*)

END_IF;

END_PROGRAM

The parallel outputs were divided in two IF clauses. Since the condition depends on the inputs, the second IF clause will never be true (because the first IF sets Out to be true) and therefore Mem will never be set. I believe that the right code should be:

IF NOT(Mem) AND NOT(Out) THEN

Out := TRUE; (*set*)

Mem := TRUE; (*set*)

END_IF;

set all outputs on the same IF clause.

Is this really an issue or does the standard for ladder logic predicts this behavior?

Thanks,

Thiago Alves

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Beremiz-devel mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/beremiz-devel

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

Hi Thiago,

Yes, I agree that this is a bug. I also agree with your interpretation of
what the resulting code should look like.

Edouard, do we have an official issue tracker for Beremiz?

Mario.

On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:

> Hello everyone!
>
> A user in the openplcproject.com forum reported an issue with the ST code
> generator for programs with parallel outputs. After a few tests, I could
> reproduce the issue with this simple program:
>
> out mem out
>
> |-----[ / ]-----[ / ]------------+------( S )------|
> |
> | mem
> |
> |------( S )------|
>
> (If the diagram doesn't show properly on your email, copy and paste it to
> notepad).
>
> This program has two boolean variables (out, mem) that are connected in
> series. If both of them are false, the program sets both to true on a
> parallel output.
>
> The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> this program is:
>
> PROGRAM My_Program
> VAR
> Mem AT %QX99.0 : BOOL;
> Out AT %QX0.0 : BOOL;
> END_VAR
>
> IF NOT(Mem) AND NOT(Out) THEN
> Out := TRUE; (*set*)
> END_IF;
> IF NOT(Mem) AND NOT(Out) THEN
> Mem := TRUE; (*set*)
> END_IF;
> END_PROGRAM
>
> The parallel outputs were divided in two IF clauses. Since the condition
> depends on the inputs, the second IF clause will never be true (because the
> first IF sets Out to be true) and therefore Mem will never be set. I
> believe that the right code should be:
>
> IF NOT(Mem) AND NOT(Out) THEN
> Out := TRUE; (*set*)
> Mem := TRUE; (*set*)
> END_IF;
>
> set all outputs on the same IF clause.
>
> Is this really an issue or does the standard for ladder logic predicts this
> behavior?
>
>
> Thanks,
>
> Thiago Alves

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

On 17-05-30 17:50, [hidden email] wrote:
>
>
>
> Hi Thiago,
>
> Yes, I agree that this is a bug. I also agree with your interpretation of
> what the resulting code should look like.
>
> Edouard, do we have an official issue tracker for Beremiz?

As far as I know, we agreed to use issue tracker on my repo [1] on
Bitbucket as official issue tracker for Beremiz.

https://bitbucket.org/skvorl/beremiz

> Mario.
>
>
> On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:
> > Hello everyone!
> >
> > A user in the openplcproject.com forum reported an issue with the ST code
> > generator for programs with parallel outputs. After a few tests, I could
> > reproduce the issue with this simple program:
> >
> > out mem out
> >
> > |-----[ / ]-----[ / ]------------+------( S )------|
> > |
> > | mem
> > |
> > |------( S )------|
> >
> > (If the diagram doesn't show properly on your email, copy and paste it to
> > notepad).
> >
> > This program has two boolean variables (out, mem) that are connected in
> > series. If both of them are false, the program sets both to true on a
> > parallel output.
> >
> > The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> > this program is:
> >
> > PROGRAM My_Program
> > VAR
> > Mem AT %QX99.0 : BOOL;
> > Out AT %QX0.0 : BOOL;
> > END_VAR
> >
> > IF NOT(Mem) AND NOT(Out) THEN
> > Out := TRUE; (*set*)
> > END_IF;
> > IF NOT(Mem) AND NOT(Out) THEN
> > Mem := TRUE; (*set*)
> > END_IF;
> > END_PROGRAM
> >
> > The parallel outputs were divided in two IF clauses. Since the condition
> > depends on the inputs, the second IF clause will never be true (because the
> > first IF sets Out to be true) and therefore Mem will never be set. I
> > believe that the right code should be:
> >
> > IF NOT(Mem) AND NOT(Out) THEN
> > Out := TRUE; (*set*)
> > Mem := TRUE; (*set*)
> > END_IF;
> >
> > set all outputs on the same IF clause.
> >
> > Is this really an issue or does the standard for ladder logic predicts this
> > behavior?
> >
> >
> > Thanks,
> >
> > Thiago Alves
>
> ------------------------------------------------------------------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

--
Best regards,
Andrey Skvortsov

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Beremiz-devel mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/beremiz-devel

signature.asc (849 bytes) Download Attachment

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

In reply to this post by Beremiz-Devel mailing list

Hi Thiago,

Can you try and replace your code with the following LD program:

out mem out mem
|
|-----[ / ]-----[ / ]-------------------( S )------( S )------|
|

I think this layout should do what you want?

I know it does not fix the bug, but it could be a work-around.

Mario.

On Tuesday 30 May 2017 17:50:44 [hidden email] wrote:

> Hi Thiago,
>
> Yes, I agree that this is a bug. I also agree with your interpretation of
> what the resulting code should look like.
>
> Edouard, do we have an official issue tracker for Beremiz?
>
>
> Mario.
>
> On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:
> > Hello everyone!
> >
> > A user in the openplcproject.com forum reported an issue with the ST code
> > generator for programs with parallel outputs. After a few tests, I could
> >
> > reproduce the issue with this simple program:
> > out mem out
> > |
> > |-----[ / ]-----[ / ]------------+------( S )------|
> > |
> > | mem
> > |
> > |------( S )------|
> >
> > (If the diagram doesn't show properly on your email, copy and paste it to
> > notepad).
> >
> > This program has two boolean variables (out, mem) that are connected in
> > series. If both of them are false, the program sets both to true on a
> > parallel output.
> >
> > The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> > this program is:
> >
> > PROGRAM My_Program
> >
> > VAR
> >
> > Mem AT %QX99.0 : BOOL;
> > Out AT %QX0.0 : BOOL;
> >
> > END_VAR
> >
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Out := TRUE; (*set*)
> >
> > END_IF;
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Mem := TRUE; (*set*)
> >
> > END_IF;
> >
> > END_PROGRAM
> >
> > The parallel outputs were divided in two IF clauses. Since the condition
> > depends on the inputs, the second IF clause will never be true (because
> > the first IF sets Out to be true) and therefore Mem will never be set. I
> >
> > believe that the right code should be:
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Out := TRUE; (*set*)
> > Mem := TRUE; (*set*)
> >
> > END_IF;
> >
> > set all outputs on the same IF clause.
> >
> > Is this really an issue or does the standard for ladder logic predicts
> > this behavior?
> >
> >
> > Thanks,
> >
> > Thiago Alves
>
> ---------------------------------------------------------------------------
> --- Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

In reply to this post by Beremiz-Devel mailing list

Hi Mario,

I tried your solution, but the ST code generator creates an invalid ST code for two coils in series. Here is the generated program:

PROGRAM My_Program

VAR

Mem AT %QX99.0 : BOOL;

Out AT %QX0.0 : BOOL;

END_VAR

IF NOT(Mem) AND NOT(Out) THEN

Mem := TRUE; (*set*)

END_IF;

IF [('NOT(', ('P::My_Program', 'contact', 4, 'negated')), ('Mem', ('P::My_Program', 'contact', 4, 'reference')), (')', ())] THEN

Out := TRUE; (*set*)

END_IF;

END_PROGRAM

It is still creating two IF clauses and the second one makes no sense. I believe there might be a parsing error somewhere.

Thanks,

Thiago Alves

Message: 4
Date: Wed, 31 May 2017 17:19:11 +0100
From: [hidden email]
To: [hidden email]
Subject: Re: [Beremiz-devel] Issue with Beremiz ST code generator
Message-ID:
<[hidden email]>
Content-Type: Text/Plain; charset="iso-8859-1"

Hi Thiago,

Can you try and replace your code with the following LD program:

out mem out mem
|
|-----[ / ]-----[ / ]-------------------( S )------( S )------|
|

I think this layout should do what you want?

I know it does not fix the bug, but it could be a work-around.

Mario.

On Tuesday 30 May 2017 17:50:44 [hidden email] wrote:
> Hi Thiago,
>
> Yes, I agree that this is a bug. I also agree with your interpretation of
> what the resulting code should look like.
>
> Edouard, do we have an official issue tracker for Beremiz?
>
>
> Mario.
>
> On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:
> > Hello everyone!
> >
> > A user in the openplcproject.com forum reported an issue with the ST code
> > generator for programs with parallel outputs. After a few tests, I could
> >
> > reproduce the issue with this simple program:
> > out mem out
> > |
> > |-----[ / ]-----[ / ]------------+------( S )------|
> > |
> > | mem
> > |
> > |------( S )------|
> >
> > (If the diagram doesn't show properly on your email, copy and paste it to
> > notepad).
> >
> > This program has two boolean variables (out, mem) that are connected in
> > series. If both of them are false, the program sets both to true on a
> > parallel output.
> >
> > The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> > this program is:
> >
> > PROGRAM My_Program
> >
> > VAR
> >
> > Mem AT %QX99.0 : BOOL;
> > Out AT %QX0.0 : BOOL;
> >
> > END_VAR
> >
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Out := TRUE; (*set*)
> >
> > END_IF;
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Mem := TRUE; (*set*)
> >
> > END_IF;
> >
> > END_PROGRAM
> >
> > The parallel outputs were divided in two IF clauses. Since the condition
> > depends on the inputs, the second IF clause will never be true (because
> > the first IF sets Out to be true) and therefore Mem will never be set. I
> >
> > believe that the right code should be:
> > IF NOT(Mem) AND NOT(Out) THEN
> >
> > Out := TRUE; (*set*)
> > Mem := TRUE; (*set*)
> >
> > END_IF;
> >
> > set all outputs on the same IF clause.
> >
> > Is this really an issue or does the standard for ladder logic predicts
> > this behavior?
> >
> >
> > Thanks,
> >
> > Thiago Alves
>
> ---------------------------------------------------------------------------
> --- Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

In reply to this post by Beremiz-Devel mailing list

On 17-05-30 21:38, [hidden email] wrote:

> On 17-05-30 17:50, [hidden email] wrote:
> >
> >
> >
> > Hi Thiago,
> >
> > Yes, I agree that this is a bug. I also agree with your interpretation of
> > what the resulting code should look like.
> >
> > Edouard, do we have an official issue tracker for Beremiz?
>
> As far as I know, we agreed to use issue tracker on my repo [1] on
> Bitbucket as official issue tracker for Beremiz.
>
> https://bitbucket.org/skvorl/beremiz
>
>

Thiago,

create to separate tickets on issue tracker for this problem.

> > Mario.
> >
> >
> > On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:
> > > Hello everyone!
> > >
> > > A user in the openplcproject.com forum reported an issue with the ST code
> > > generator for programs with parallel outputs. After a few tests, I could
> > > reproduce the issue with this simple program:
> > >
> > > out mem out
> > >
> > > |-----[ / ]-----[ / ]------------+------( S )------|
> > > |
> > > | mem
> > > |
> > > |------( S )------|
> > >
> > > (If the diagram doesn't show properly on your email, copy and paste it to
> > > notepad).
> > >
> > > This program has two boolean variables (out, mem) that are connected in
> > > series. If both of them are false, the program sets both to true on a
> > > parallel output.
> > >
> > > The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> > > this program is:
> > >
> > > PROGRAM My_Program
> > > VAR
> > > Mem AT %QX99.0 : BOOL;
> > > Out AT %QX0.0 : BOOL;
> > > END_VAR
> > >
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Out := TRUE; (*set*)
> > > END_IF;
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Mem := TRUE; (*set*)
> > > END_IF;
> > > END_PROGRAM
> > >
> > > The parallel outputs were divided in two IF clauses. Since the condition
> > > depends on the inputs, the second IF clause will never be true (because the
> > > first IF sets Out to be true) and therefore Mem will never be set. I
> > > believe that the right code should be:
> > >
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Out := TRUE; (*set*)
> > > Mem := TRUE; (*set*)
> > > END_IF;
> > >
> > > set all outputs on the same IF clause.
> > >
> > > Is this really an issue or does the standard for ladder logic predicts this
> > > behavior?
> > >
> > >
> > > Thanks,
> > >
> > > Thiago Alves
> >
> > ------------------------------------------------------------------------------
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > _______________________________________________
> > Beremiz-devel mailing list
> > [hidden email]
> > https://lists.sourceforge.net/lists/listinfo/beremiz-devel
>
> --
> Best regards,
> Andrey Skvortsov
>
>

> ------------------------------------------------------------------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot

> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

--
Best regards,
Andrey Skvortsov

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Beremiz-devel mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/beremiz-devel

signature.asc (849 bytes) Download Attachment

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

In reply to this post by Beremiz-Devel mailing list

Hi Andrey,

Sorry, I saw your message on Beremiz-dev, but I got quite busy these last days and never created the ticket. I'll do it today.

Thanks,

Thiago Alves

On Jun 7, 2017 8:46 AM, "Andrey Skvortsov" <[hidden email]> wrote:

On 17-05-30 21:38, [hidden email] wrote:

> On 17-05-30 17:50, [hidden email] wrote:
> >
> >
> >
> > Hi Thiago,
> >
> > Yes, I agree that this is a bug. I also agree with your interpretation of
> > what the resulting code should look like.
> >
> > Edouard, do we have an official issue tracker for Beremiz?
>

> As far as I know, we agreed to use issue tracker on my repo [1] on
> Bitbucket as official issue tracker for Beremiz.
>
> https://bitbucket.org/skvorl/beremiz
>
>

Thiago,

create to separate tickets on issue tracker for this problem.

> > Mario.
> >
> >
> > On Tuesday 30 May 2017 17:30:05 [hidden email] wrote:
> > > Hello everyone!
> > >
> > > A user in the openplcproject.com forum reported an issue with the ST code
> > > generator for programs with parallel outputs. After a few tests, I could
> > > reproduce the issue with this simple program:
> > >
> > > out mem out
> > >
> > > |-----[ / ]-----[ / ]------------+------( S )------|
> > > |
> > > | mem
> > > |
> > > |------( S )------|
> > >
> > > (If the diagram doesn't show properly on your email, copy and paste it to
> > > notepad).
> > >
> > > This program has two boolean variables (out, mem) that are connected in
> > > series. If both of them are false, the program sets both to true on a
> > > parallel output.
> > >
> > > The problem is that the ST code generated by Beremiz (PLCopen Editor) for
> > > this program is:
> > >
> > > PROGRAM My_Program
> > > VAR
> > > Mem AT %QX99.0 : BOOL;
> > > Out AT %QX0.0 : BOOL;
> > > END_VAR
> > >
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Out := TRUE; (*set*)
> > > END_IF;
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Mem := TRUE; (*set*)
> > > END_IF;
> > > END_PROGRAM
> > >
> > > The parallel outputs were divided in two IF clauses. Since the condition
> > > depends on the inputs, the second IF clause will never be true (because the
> > > first IF sets Out to be true) and therefore Mem will never be set. I
> > > believe that the right code should be:
> > >
> > > IF NOT(Mem) AND NOT(Out) THEN
> > > Out := TRUE; (*set*)
> > > Mem := TRUE; (*set*)
> > > END_IF;
> > >
> > > set all outputs on the same IF clause.
> > >
> > > Is this really an issue or does the standard for ladder logic predicts this
> > > behavior?
> > >
> > >
> > > Thanks,
> > >
> > > Thiago Alves
> >
> > ------------------------------------------------------------------------------
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > _______________________________________________
> > Beremiz-devel mailing list
> > [hidden email]
> > https://lists.sourceforge.net/lists/listinfo/beremiz-devel
>

> --
> Best regards,
> Andrey Skvortsov
>
>

> ------------------------------------------------------------------------------

> Check out the vibrant tech community on one of the world's most
> engaging tech sites, Slashdot.org! http://sdm.link/slashdot

> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

--
Best regards,
Andrey Skvortsov

Beremiz-Devel mailing list

Re: [Beremiz-devel] Issue with Beremiz ST code generator

On 17-06-07 08:52, [hidden email] wrote:
> Hi Andrey,
>
> Sorry, I saw your message on Beremiz-dev, but I got quite busy these last
> days and never created the ticket. I'll do it today.
>
>
> Thanks,
>
> Thiago Alves

Thiago, could you please create two separate tickets.

One for the problem where logic is wrong after code generation.

|-----[ / ]-----[ / ]------------+------( S )------|
|
| mem
|
|------( S )------|

And one for the problem when incorrect ST code is generated.

|-----[ / ]-----[ / ]--------------( S )----( S )--|

>
>
> On Jun 7, 2017 8:46 AM, "Andrey Skvortsov" <[hidden email]>
> wrote:
>
> On 17-05-30 21:38, [hidden email] wrote:
> > On 17-05-30 17:50, [hidden email] wrote:
> > >
> > >
> > >
> > > Hi Thiago,
> > >
> > > Yes, I agree that this is a bug. I also agree with your interpretation
> of
> > > what the resulting code should look like.
> > >
> > > Edouard, do we have an official issue tracker for Beremiz?
> >
> > As far as I know, we agreed to use issue tracker on my repo [1] on
> > Bitbucket as official issue tracker for Beremiz.
> >
> > https://bitbucket.org/skvorl/beremiz
> >
> >
>
> Thiago,
>
> create to separate tickets on issue tracker for this problem.
>
>
> > > Mario.
> > >
> > >
> > > On Tuesday 30 May 2017 17:30:05 [hidden email]
> wrote:
> > > > Hello everyone!
> > > >
> > > > A user in the openplcproject.com forum reported an issue with the ST
> code
> > > > generator for programs with parallel outputs. After a few tests, I
> could
> > > > reproduce the issue with this simple program:
> > > >
> > > > out mem out
> > > >
> > > > |-----[ / ]-----[ / ]------------+------( S )------|
> > > > |
> > > > | mem
> > > > |
> > > > |------( S )------|
> > > >
> > > > (If the diagram doesn't show properly on your email, copy and paste
> it to
> > > > notepad).
> > > >
> > > > This program has two boolean variables (out, mem) that are connected
> in
> > > > series. If both of them are false, the program sets both to true on a
> > > > parallel output.
> > > >
> > > > The problem is that the ST code generated by Beremiz (PLCopen Editor)
> for
> > > > this program is:
> > > >
> > > > PROGRAM My_Program
> > > > VAR
> > > > Mem AT %QX99.0 : BOOL;
> > > > Out AT %QX0.0 : BOOL;
> > > > END_VAR
> > > >
> > > > IF NOT(Mem) AND NOT(Out) THEN
> > > > Out := TRUE; (*set*)
> > > > END_IF;
> > > > IF NOT(Mem) AND NOT(Out) THEN
> > > > Mem := TRUE; (*set*)
> > > > END_IF;
> > > > END_PROGRAM
> > > >
> > > > The parallel outputs were divided in two IF clauses. Since the
> condition
> > > > depends on the inputs, the second IF clause will never be true
> (because the
> > > > first IF sets Out to be true) and therefore Mem will never be set. I
> > > > believe that the right code should be:
> > > >
> > > > IF NOT(Mem) AND NOT(Out) THEN
> > > > Out := TRUE; (*set*)
> > > > Mem := TRUE; (*set*)
> > > > END_IF;
> > > >
> > > > set all outputs on the same IF clause.
> > > >
> > > > Is this really an issue or does the standard for ladder logic
> predicts this
> > > > behavior?
> > > >
> > > >
> > > > Thanks,
> > > >
> > > > Thiago Alves
> > >
> > > ------------------------------------------------------------
> ------------------
> > > Check out the vibrant tech community on one of the world's most
> > > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > > _______________________________________________
> > > Beremiz-devel mailing list
> > > [hidden email]
> > > https://lists.sourceforge.net/lists/listinfo/beremiz-devel
> >
> > --
> > Best regards,
> > Andrey Skvortsov
> >
> >
>
>
>
> > ------------------------------------------------------------
> ------------------
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
>
> > _______________________________________________
> > Beremiz-devel mailing list
> > [hidden email]
> > https://lists.sourceforge.net/lists/listinfo/beremiz-devel
>
>
> --
> Best regards,
> Andrey Skvortsov

> _______________________________________________
> Beremiz-devel mailing list
> [hidden email]
> https://lists.sourceforge.net/lists/listinfo/beremiz-devel

--
Best regards,
Andrey Skvortsov

------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
Beremiz-devel mailing list
[hidden email]
https://lists.sourceforge.net/lists/listinfo/beremiz-devel

signature.asc (849 bytes) Download Attachment